1. Field of the Invention
The present invention relates to fabrication of integrated circuits and, in particular, to structure and methods for verifying photolithographic exposure during integrated circuit fabrication.
2. Discussion of the Prior Art
As is well known, photolithographic techniques are utilized in the fabrication of integrated circuits to define the extremely small geometries required in such circuits. A basic step in the photolithographic fabrication of integrated circuits involves coating a substrate, usually silicon, with a thin layer of photosensitive material called photoresist or simply resist. The integrated circuit geometric feature which is desired to be created in the substrate is transferred to the photoresist from a pattern on a glass plate or "mask" by any one of a variety of well known optical exposure techniques. The transferred pattern is then etched onto the photoresist using a solvent to remove the exposed portions, revealing corresponding portions of the underlying substrate. These exposed portions of the substrate may then be processed. For example, active dopant atoms can be introduced to selected region of the substrate to alter the electrical characteristics of these regions, or the underlying insulating or conductive layers may be etched. The process is then repeated for as many layers as are required to fabricate the desired circuit.
One of the problems associated with the exposure process is the possibility of under- or over-exposure of the photoresist. This can cause incomplete transfer of the pattern or inaccurate line widths, causing reliability or functionality problems One solution to the problem is to incorporate a line on the mask pattern, separate and apart from the integrated circuit feature This so-called "critical dimension line is then microscopically examined after exposure of the photoresist. The width of the line provides information regarding the degree of exposure. Obtaining a measurement equal to the expected line width means that proper exposure has been obtained. If the line is thinner than expected, an overexposed condition exists. If the line is broader than expected, an underexposed condition exists.
An ancillary problem in measuring the critical dimension line width is that high powered microscopes are often required. Such microscopes are expensive and not always readily available for on-the-spot measurement during a circuit fabrication process, or if they are available, there is a high demand for its use such that delays in measurement often occur.
Another problem in the fabrication process is the difficulty obtaining registration of successive layers of circuit features. As successive layers are fabricated, different masks are used to create the desired circuit features. In order to function properly, the circuit features of each layer must be vertically aligned in order to accurately interconnect, or separate, as appropriate, the added portion of exposed resist
Therefore, it would be desirable to provide an improved method for verifying the proper exposure of a photoresist pattern on a silicon wafer during integrated circuit fabrication. Such a method should quickly and efficiently check the critical dimensions of integrated circuit features as transferred by lithography.
It would also be desirable to provide a method for verifying registration of successive layers of exposed features on the same structure as is used for critical dimension verification to save space on the wafer and speed inspection time.